Design and Implementation of a Bit Synchronous Clock Extraction Circuit

Computer & Telecommunication

2019, Vol. 1

Issue (1-2): 13-16 DOI:

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Design and Implementation of a Bit Synchronous Clock Extraction Circuit

YUE Zhi-qiYANG Chen-xiSUN Ling LI Zhu

Shanxi Normal University

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Abstract The scheme realizes the extraction of bit synchronization clock based on FPGA under the condition of analyzing signal transmission in simulation channel. Among them, the shaping circuit uses hysteresis comparator to improve the anti-interference ability of the system. The average design of high and low level counting solves the problem of different widths ofhigh and low level caused by the front circuit and improves the accuracy and stability of clock extraction. Through measurement, the error of the extracted bit synchronization clock is less than 1%, and its jitter is less than 10% of a bit synchronization cycle.

Key words： bit synchronization clock FPGA digital phase-locked-loop m sequence

Published: 31 July 2019

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YUE Zhi-qiYANG Chen-xiSUN Ling LI Zhu. Design and Implementation of a Bit Synchronous Clock Extraction Circuit. Computer & Telecommunication, 2019, 1(1-2): 13-16.

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http://www.computertelecom.com.cn/EN/ OR http://www.computertelecom.com.cn/EN/Y2019/V1/I1-2/13

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