This paper introduces a method of image data transmission between AM5706 and FPGA through VIP(Video Input Port) interface. This method is a key technology of bill image scanning module. Bill image scanning module can collect two CIS image sensor signals, which are sent to FPGA for gray value compensation preprocessing after analog-to-digital conversion. FPGA accumulates a complete line of image data and outputs it to VIP interface of AM5706. Each time AM5706 VIP device receives a full image data, it will trigger a CPU interrupt. Compared with the traditional EMIF parallel bus + EMDA method, of which can only receive one line of image data at a time, using VIP interface can greatly reduce the CPU interrupt frequency and CPU resource utilization, which is of great significance to improve the system performance and reduce the hardware cost.