Machine Learning Empowered EDA Backend Design: Technological Breakthroughs and Future Prospects

YANG Cheng-cheng

Computer & Telecommunication ›› 2025, Vol. 1 ›› Issue (4) : 1-6.

Computer & Telecommunication ›› 2025, Vol. 1 ›› Issue (4) : 1-6.

Machine Learning Empowered EDA Backend Design: Technological Breakthroughs and Future Prospects

  • YANG Cheng-cheng
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Abstract

In the digital age, chips, as the core of information technology, have become a key indicator of a country's technological strength. Electronic Design Automation (EDA) tools play a crucial role in chip design. However, there is a significant gap between China and international advanced levels in the development of EDA tools, especially in the field of digital chip backend design. This paper reviews the current applications of machine learning in EDA backend design, exploring technological breakthroughs in optimizing layout and routing, power noise verification, and library characterization. It also discusses future development trends. Empowered by machine learning, it is expected that China's EDA tool development capabilities will be enhanced, promoting the independent and high-quality development of the chip industry.

Key words

machine learning / EDA backend design / layout and routing / power noise verification / library characterization

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YANG Cheng-cheng. Machine Learning Empowered EDA Backend Design: Technological Breakthroughs and Future Prospects[J]. Computer & Telecommunication. 2025, 1(4): 1-6

References

[1] 魏少军.中国芯片设计业要自强不息[EB/OL].(2024-12-13). https://news. sohu. com/a/836219340_121124366.
[2] Li X,Hu Z,Zhang Y,et al.Application of Machine Learning in EDA:A Survey[J].Proceedings of the IEEE, 2019,107(6):1230-1245.
[3] 陈浩,郑刚,赵晓东.机器学习在电源噪声验证中的应用进展[J].集成电路技术,2021,38(4):45-52.
[4] 刘鹏,周晨.基于卷积神经网络的EDA工具自动化布局布线优化技术[J].计算机工程与应用,2020, 56(11):145-150.
[5] 赵天宇,王磊,刘峰.基于机器学习的库特征提取与优化方法[J].电子与信息学报,2021,43(12):2992-3000.
[6] 王旭,陈明,张磊.基于机器学习的EDA工具链优化研究[J].电子设计工程,2022,30(7):56-63.
[7] 张威,周浩,黄晓峰.机器学习在EDA工具后端设计中的应用与挑战[J].半导体技术,2020,45(10):74-80.
[8] 王毅,刘翔.基于深度学习的EDA工具自动化验证技术研究[J].集成电路设计与应用,2019,21(6):35-42.
[9] Olofsson A.Intelligent Design of Electronic Assets (IDEA) and Posh Open Source Hardware.https://www.darpa.mil/attachments/eri_design_proposers_day.pdf.
[10] Lee Y,Waterman A,Cook H,et al.An Agile Approach to Building RISC-V Microprocessors[J].IEEE Micro,2016,36(2):8-20.
[11] 余子濠,刘志刚,李一苇,等.芯片敏捷开发实践:标签化 RISC-V[J].计算机研究与发展,2019,56(1):35-48.
[12] Kahng A.Reducing time and effort in IC implementation:a roadmap of challenges and solutions[C]//Proc.IEEE Design Automation Conference,2018,1-6.
[13] Pandey M.Machine learning and systems for building the next generation of EDA tools[C]//Proc.IEEE Asia and South Pacific Design Automation Conference,2018,411-415.
[14] Bertacco V.Humans for EDA and EDA for humans[C]//Proc.IEEE Design Automation Conference,2012:729-733.
[15] Haritan E,Kuehlmann A,Jones T,et al.EDA in flux -Should I stay or should I go?[C]//Proc.IEEE Design Automation Conference,2009:91-92.
[16] Lin Y,Dhar S,Li W,et al.DREAMPlace:Deep learning toolkit-enabled GPU acceleration for modern VLSI placement[C]//Proc.IEEE Design Automation Conference,2019,1-6.
[17] Zhuo C,Unda K,Shi Y,et al.A novel cross-layer framework for early-stage power delivery and architecture co-exploration[C]//Proc.IEEE Design Automation Conference,2016,1-6.
[18] Zhuo C,Agarwal K,Blaauw D,et al.Active learning framework for post-silicon variation extraction and test cost reduction[C]//Proc.IEEE International Conference on Computer-Aided Design,2010,508-515.
[19] Chen J,Kuang J,Zhao G,et al.PROS 2.0:A plug-in for routability optimization and routed wirelength estimation using deep learning[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2022,42(1):164-177.
[20] Liu S,Wang Z,Liu F,et al.Concurrent sign-off timing optimization via deep Steiner points refinement[C]//2023 60th ACM/IEEE Design Automation Conference (DAC).IEEE,2023:1-6.
[21] Lin Z,Zhang H,Gao P,et al.GNN-Based Timing Prediction in Pre-Routing Stage With Multi-Task Learning Strategy[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2025.
[22] Lingfei L I,Tieru W U.Automatic spectral method of mesh segmentation based on fiedler residual[J].Chinese Journal of Electronics,2021,30(3):426-436.
[23] Bai T,Deng Z,Cao P.Cell Library Characterization for Composite Current Source Models Based on Gaussian Process Regression and Active Learning[C]//Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD.2024:1-7.
[24] Cheng X,Ye Y,He G,et al.Heterogeneous Graph Attention Network Based Statistical Timing Library Characterization with Parasitic RC Reduction[C]//2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC).IEEE,2024:171-176.
[25] Zhong R,Du X,Kai S,et al.LLM4EDA:Emerging Progress in Large Language Models for Electronic Design Automation[J].CoRR,2024.
[26] Pan J,Chang C C,Xie Z,et al.EDALearn:A Comprehensive RTL-to-Signoff EDA Benchmark for Democratized and Reproducible ML for EDA Research[J].arXiv preprint arXiv:2312.01674,2023.
[27] Wu H,He Z,Zhang X,et al.Chateda:A large language model powered autonomous agent for eda[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2024.

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