Basic Usage of Configuration Statements in VHDL

Computer & Telecommunication

2015, Vol. 1

Issue (10): 77-78 DOI:

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Basic Usage of Configuration Statements in VHDL

Luo Yu，Yue Miao，Fu Rao

West China Normal University

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Abstract In the VHDL language, a configuration can be associated with a specific structure to a certain entity. Usually in the VHDL project, the configuration statements can be specified or attached to a structure, and it can let an entity configure different structures for different functions or simulations. This paper introduces the basic form of the configuration statements and the basic usage of the configuration statements by example.

Key words： VHDL configuration entity structure

Published: 09 November 2017

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	Luo Yu
	Yue Miao
	Fu Rao

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Luo Yu, Yue Miao, Fu Rao. Basic Usage of Configuration Statements in VHDL. Computer & Telecommunication, 2015, 1(10): 77-78.

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https://www.computertelecom.com.cn/EN/ OR https://www.computertelecom.com.cn/EN/Y2015/V1/I10/77

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