Abstract：As the working frequency of the integrated circuits increased, more kinds of package have been used in high speed
electronic system. The electronic performance of the package plays a more important role in the system than ever. Engineers will always
meet the situation that the layers of the base-board must be reduced or the number of the power pins is limited, however the IC
packaged in Wirebond may still be worked in high frequency. It’s very difficult to confirm the IC’s working condition when the performance
of package is unclear, which will cause the delay of product extension. In order to improve the efficiency of the design, it’
s necessary to find the margin of the design through the emulation of the“Chip-Package-Board”system. Based on this reason, the
parasitical parameter of the package must be evaluated and used in the system emulation. This paper introduces a fast method to
build the package model.
侯建平, 张家训, 何凯. 一种封装管壳快速建模方法[J]. 电脑与电信, 2017, 1(6): 34-36.
Hou Jianping, Zhang Jiaxun, He Kai. A Fast Method of Model Building of the Package. Computer & Telecommunication, 2017, 1(6): 34-36.
2017, Vol. 1 
