随着芯片工作频率越来越高，越来越多的封装被应用于高速电子系统。IC 封装的电性能在整个系统性能上 起着越来越重要的作用。工程师经常会遇到基板层数减少或者电源地管脚数量有限，但以Wirebond 形式封装的IC 仍要工作 在超高的频率。在封装电性能未知的情况下要确认整个芯片是否能正常工作将非常困难，这将会影响产品推向市场的时间。 为了提高设计效率及成功率，有必要从Chip-Package-Board 的系统仿真中找出设计的盈余。基于此原因，需要评估出封装管 壳的寄生参数并用于系统的仿真。本文介绍了一种管壳建模的快速方法。

As the working frequency of the integrated circuits increased, more kinds of package have been used in high speed electronic system. The electronic performance of the package plays a more important role in the system than ever. Engineers will always meet the situation that the layers of the base-board must be reduced or the number of the power pins is limited, however the IC packaged in Wirebond may still be worked in high frequency. It’s very difficult to confirm the IC’s working condition when the performance of package is unclear, which will cause the delay of product extension. In order to improve the efficiency of the design, it’ s necessary to find the margin of the design through the emulation of the“Chip-Package-Board”system. Based on this reason, the parasitical parameter of the package must be evaluated and used in the system emulation. This paper introduces a fast method to build the package model.