随着集成电路制造工艺发展到90nm以下，纳米级效应对时序的影响越来越显著。对于全定制数字电路，精确 评估内部信号完整性（SI）尤为重要。高速SRAM IP 采用65nm工艺全定制设计，我们选择Synopsys 公司的NanoTime 来分析 信号完整性。本文详细介绍了NanoTime静态时序分析、SI 分析、时序模型提取在SRAM IP设计中的应用。

As the IC process below 90nm, nanometer effect is more evident. For custom digital logic, how to analyze Signal Integrity (SI) is very important. The high speed SRAM IP is designed by 65nm process. Our design team used NanoTime for signal integrity checking. This paper introduces NanoTime application of static timing analysis, timing model generation and SI analysis in the high speed SRAM IP design.