本论文提出一种通过基准电压来减小延时的IO 设计方法，设计出具高速特性的IO 模块，从而满足高速 SRAM产品的使用需求。该模块主要的设计思路为：通过基准电压提供一个中间态电压，通过中间态电压快速响应，减小IO 的延时。通过HSPICE仿真表明，这款电路能满足200Mhz SRAM 需求，并通过流片，验证此结构是可行的。

This paper introduces a design method through the bandgap voltage to reduce the delay of IO, presents a design of IO with high speed, which meets the requirement of high speed SRAM products. The main design idea of this module is : With bandgap supplying a middle stage voltage，the module can response fast, which reduces the delay of IO. Through the HSPICE simulation results, the demand of 200 Mhz SRAM can be satisfied by this circuit, and the module has been proved reliable by taping out.