FPGA 设计规模和复杂度的急剧增加使得对其测试的难度提高。本文研究UVM（通用验证方法学）架构和特 点，采用UVM 搭建验证平台，以TS101 作为上位机、FPGA 作为其接口控制功能为例，验证FPGA 逻辑设计的正确性。

Dramatically increasing in the scale and complexity of FPGA design makes it more difficult to be tested. This article studies the structure and characteristics of universal verification methodology (UVM). It uses UVM to set up the verification platform, taking the TS101 as the host computer and FPGA as function of the interface control, verifying the correctness of the FPGA logic design.