基于可编程逻辑器件，设计了一种针对横向多通道像素并行输出特点的哈特曼波前传感器的实时质心运算流 水线架构。该架构由乘法器单元、累加单元和除法单元组成，各个单元内运算器的数目可根据输出通道数和输出像素顺序自 由配置。对于一帧图像的质心运算，经过该架构处理后延时仅为对最后输出的一个像素处理所需时间。仿真结果表明，对于 以80MHz 的时钟频率，横向8 个像素并行输出的哈特曼波前传感器，其运算延时不超过0.5μs。

In this paper, a real-time pipeline centroid calculating structure based on programmable logic devices is designed for Hartmann wavefront sensor with horizontal multi-channel pixel output. The structure is composed of multiplier groups, accumulation cells and dividers. The cells are designed according to the number of output channels and the output pixels’sequence. The centroid calculation latency in one frame is only the calculation time needed for the pixels output at the last pixel clock. In the simulation, when output channels’number is 8 and pixels output at 80MHz clock, centroid calculation latency is less than 0.5μs.