在VHDL 语言中，配置可以把特定的结构体关联到（或指定给）一个确定的实体。通常在VHDL 工程中，配置 语句可以为实体指定或配属一个结构体，让一个实体配置不同的结构体以使其具有不同的功能或比较不同结构体的仿真差别 等。本文介绍了配置语句的基本格式，并通过例子讲解配置语句的基本用法。

In the VHDL language, a configuration can be associated with a specific structure to a certain entity. Usually in the VHDL project, the configuration statements can be specified or attached to a structure, and it can let an entity configure different structures for different functions or simulations. This paper introduces the basic form of the configuration statements and the basic usage of the configuration statements by example.