介绍了一种AM5706通过VIP接口与FPGA图像数据传输的实现方法，该方法是票据图像扫描模块的一个关键 技术，票据图像扫描模块可采集两级CIS图像传感器信号，经模数转换后送入FPGA进行灰度值补偿预处理，FPGA积累完整 一行图像数据后，输出到AM5706的VIP接口。AM5706 VIP设备每接收到一幅完整的图像数据，才会触发一次CPU中断，相 比传统EMIF并行总线+EMDA方法的每次只能接收一行图像数据，采用VIP接口传输图像数据可极大减少CPU中断次数、降 低CPU资源使用率，这对提升系统性能和降低硬件成本都具有重要意义。

This paper introduces a method of image data transmission between AM5706 and FPGA through VIP(Video Input Port) interface. This method is a key technology of bill image scanning module. Bill image scanning module can collect two CIS image sensor signals, which are sent to FPGA for gray value compensation preprocessing after analog-to-digital conversion. FPGA accumulates a complete line of image data and outputs it to VIP interface of AM5706. Each time AM5706 VIP device receives a full image data, it will trigger a CPU interrupt. Compared with the traditional EMIF parallel bus + EMDA method, of which can only receive one line of image data at a time, using VIP interface can greatly reduce the CPU interrupt frequency and CPU resource utilization, which is of great significance to improve the system performance and reduce the hardware cost.